- Synopsys (Nasdaq: SNPS) announced new innovations with TSMC for next-generation AI, HPC, and advanced semiconductor systems.
- Collaborations include A14 design enablement across digital and analog flows, and agentic AI capabilities for analog, digital, and multi-die workflows.
- Synopsys enabled IVR multi-die designs on TSMC CoWoS technology for power efficiency.
- Co-packaged optics design on TSMC COUPE technology is supported via photonic and electronic co-design flow.
- On TSMC N2P process, Synopsys achieved IP enablement and tape-out milestones including PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and SLM PVT monitoring IP.
- Synopsys demonstrated UCIe-A 32G/40G silicon on N3P test chip with CoWoS-S interposer; completed 64G UCIe IP tape-outs on 2nm and 3nm nodes.
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